Computer System Lab
Department of Informatics
School of Engineering
Technological Institute of Athens
12210 Egaleo, Athens,
Greece
+302105385394
+302105910975
Email: cefsta@teiath.gr
"High-Speed Regular-Layout Modulo 2n-1 Adders". L. Kalampoukas, D. Nikolos, C. Efstathiou, H. T. Vergos, J. Kalamatianos, World Patent # WO0208885
1. C. Efstathiou, C. Halatsis, "Efficient modular design of m-out-of-2m TSC checkers, for m = 2k-1, k > 2", Electronics Letters, vol. 21, no. 23, pp.1083-1084, Nov. 1985.
2. C. Efstathiou, "Efficient MOS implementation of totally self-checking two-rail code checkers", International Journal of Electronics, vol. 68, no. 2, pp. 259-264, Feb. 1990.
3. A. Paschalis, C. Efstathiou, C. Halatsis, "An efficient TSC 1-out-of-3 code checker", IEEE Transactions on Computers, vol. 39, no. 3, pp. 407-411, March 1990.
4. C. Efstathiou, D. Nikolos, J. Kalamatianos, "Area-Time efficient modulo 2n-1 adder design", IEEE Transactions on Circuits and Systems-II, vol. 41, no. 7, pp. 463-467, July 1994.
5. L. Kalamboukas, D. Nikolos, C. Efstathiou, H. T. Vergos, J. Kalamatianos, "High-Speed Regular-Layout Modulo 2n-1 Adders", IEEE Transactions on Computers, Special Issue on Computer Arithmetic, vol. 49, no. 7, pp. 673-680, July 2000.
6. H. T. Vergos, C. Efstathiou, D. Nikolos, "Diminished-One Modulo 2n+1 Adder Design", IEEE Transaction on Computers, vol. 52, no. 12, pp. 1389-1399, December 2002.
7. C. Efstathiou, H. T. Vergos, and D. Nikolos, "Handling zero in diminished-one modulo 2n+1 adders", International Journal of Electronics, vol. 90, no. 2, pp. 133-144, Feb. 2003.
8. Th. Haniotakis, Y. Tsiatouhas, C. Efstathiou, D. Nikolos, "Domino-CMOS Strongly Code-Disjoint and Strongly Fault-Secure 2-out-of-3 and 1-out-of-3 Code Checkers", International Journal of Electronics, vol. 90, no. 2, pp. 145-158, Feb. 2003.
9. H. T. Vergos, and D. Nikolos, C. Efstathiou, "Deterministic BIST for RNS Adders", IEEE Transaction on Computers, vol. 52, no. 7, pp. 896-906, July 2003.
10. C. Efstathiou, H. T. Vergos, and D. Nikolos, "Modulo 2n+1 Adder Design Using Select-Prefix Blocks", IEEE Transaction on Computers, vol. 52, no. 11, pp. 1399- 1406, Nov. 2003.
11. C. Efstathiou, H. T. Vergos, and D. Nikolos, "Modulo 2n-1 Modified Booth Multipliers", IEEE Transactions on Computers, vol. 53, no. 3, pp. 370-374, March 2004.
12. C. Efstathiou, H. T. Vergos, and D. Nikolos, "Fast parallel-prefix modulo 2n+1 adders", IEEE Transactions on Computers, pp. 1211-1216, vol. 53, no. 9, September 2004.
13. C. Efstathiou, H. T. Vergos, G. Dimitrakopoulos, and D. Nikolos, "Efficient Diminished-1 Modulo 2n+1 Multipliers", IEEE Transactions on Computers, pp. Oct. 2005.
14. H. T. Vergos, C. Efstathiou, "Diminished-1 Modulo 2n+1 squarer design", IEE Proceedings on Computers and Digital Techniques, vol.152, no. 5, pp. 561-566, Oct. 2005.
15. H. T. Vergos, and C. Efstathiou, "On the Design of Efficient Modular Adders", Journal of Circuits, Systems and Computers, vol. 14, no. 5, pp. 965-972, Oct. 2005.
16. N. Sklavos, K. Touliou, and C. Efstathiou, "Security & Privacy Architectural Modules: On the Hardware & Software Integration Platforms", WSEAS Transactions on Information Science and Applications, vol. 3, no 5, pp. 965-971, May 2006.
17. H. T. Vergos, and C. Efstathiou, "On the Design of Efficient Modulo 2n+1 Multipliers", ΙΕT Proceedings on Computers and Digital Techniques, vol.1, no.1, pp. 49-57, Jan. 2007.
18. Th. Haniotakis, Y. Tsiatouhas, D. Nikolos, C. Efstathiou, "Testable Designs of Multiple Precharged Domino Circuits", ΙΕΕΕ Transaction on VLSI, vol. 15, no. 4, pp. 461-465, April 2007.
19. H. T. Vergos, C. Efstathiou, "Unifying Approach for Weighted and Diminished-1 Modulo 2n+1 Adders", IEEE Transactions on Circuits and Systems-II, vol. 55, no. 10, pp. 1041–1045, October 2008.
20. H. T. Vergos, C. Efstathiou, "Efficient Modulo 2n+1 Adder Architectures", Integration, the VLSI Journal, vol. 42, no. 2, pp. 149–157, February 2009.
21. H. T. Vergos, D. Bakalis and C. Efstathiou, "Fast Modulo 2n+1 Multi-Operand Adders and Residue Generators", Integration, the VLSI Journal, vol. 43, no. 1, pp. 42–48, January 2010.
22. A. Bogris, D. Syvridis, and C. Efstathiou, "Noise Properties of Degenerate Dual Pump Phase Sensitive Amplifiers", IEEE Journal of Lightwave Technology, vol. 28, no. 8, pp. 1209-1217, April 2010.
23. I. Voyiatzis, C. Efstathiou, "An Efficient Architecture for Accumulator-Based Test Generation of SIC pairs", Microelectronics Journal, vol. 41, no. 8, pp. 487-493, August 2010.
24. I. Voyiatzis, H. Antonopoulou, C. Efstathiou, “A Low-Cost Optimal Time Sic Pair Generator”, Radioelectronics & Informatics, no. 4 (51), September–December 2010.
25. I. Voyiatzis, C. Efstathiou, H. Antonopoulou, A. Milidonis, “An Arithmetic Module-Based BIST Architecture For Two-Pattern Testing”, IET Computers & Digital Techniques (accepted for publication)
26. C. Efstathiou, N. Moschopoulos, I. Voyiatzis and K. Pekmestzi, "On the design of modulo 2n+1 dot product and generalized multiply-add units", Electrical and Computer Engineering (accepted for publication)
K. Katzourakis, G. Kormentzas, K. Kontovasilis and C. Efstathiou, "A Virtual Signaling Protocol for Transparently Embedding Advanced Traffic Control and Resource Management Functionality in ATM Core Networks", Lecture Notes in Computer Science, pp. 259–271, vol. 2839, 2003.
1. C. Efstathiou, C. Halatsis, "Modular realization of totally self-checking checkers for m-out-of-n codes", in Proceedings of the 13th IEEE International Symposium on Fault-Tolerant Computing, pp. 154-161, Milan, Italy, June 1983.
2. C. Efstathiou, C. Halatsis, "Modular design of totally self-checking checkers for 1-out-of-n codes", in Proceedings of the second GI/NTG/GMR Conference on Fault-Tolerant Computing Systems, pp. 164-176, Bonn, Germany, Sept. 1984.
3. T. Haniotakis, Y. Tsiatouhas, C. Efstathiou, D. Nikolos, "Novel Domino-CMOS Strongly Code Disjoint and Strongly Fault-Secure 1-out-of-3 and 2-out-of-3 Code Checkers", in Proc. of the 5th IEEE International On-Line Testing Workshop (IOLTW), pp. 174-178, Rodos, Greece, July 1999.
4. T. Haniotakis, Y. Tsiatouhas, D. Nikolos, C. Efstathiou, "On Testability of Multiple Precharged Domino Logic", in Proc. of the IEEE International Symposium on Quality of Electronic Design (ISQED’00), pp. 299-303, San Jose, California, March 2000.
5. C. Efstathiou, H. T. Vergos, "Modified Booth 1’s complement and modulo 2n-1 multipliers", in Proc. of 7th IEEE International Conference on Electronics, Circuits and Systems (ICECS), vol. II, pp. 637-640, Beirut, Lebanon, Dec. 2000.
6. H. T. Vergos D. Nikolos, M. Bellos, C. Efstathiou", Α Formal Test Set for RNS Adders and an Εfficient BIST Scheme", in Proc. of the 2nd IEEE Latin-American Testing Workshop (LATW), pp. 242-247, Cancun, Mexico, Feb. 2001.
7. H. T. Vergos, C. Efstathiou, D. Nikolos, "High-Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands", in Proc. of the 15th IEEE Computer Arithmetic Symposium, 2001, pp. 211-217, Veil, Colorado, June 2001.
8. Y. Tsiatouhas, T. Haniotakis, D. Nikolos, C. Efstathiou, "Concurrent Detection of Temporary Faults Based on Current Monitoring", in Proc. of the ΙΕΕΕ International On-Line Testing Workshop, pp. 106-110, Taormina, Italy, June 2001.
9. C. Efstathiou, H. T. Vergos, D. Nikolos, "On the Design of modulo 2n±1 adders", in Proc. of the 8th IEEE International Conference on Electronics, Circuits and Systems, (ICECS’01), vol. I, pp. 517-520, Malta, Sept. 2001.
10. C. Efstathiou, H. T. Vergos, D. Nikolos. "Ling Adders in CMOS standard cell technologies", in Proc.of the 9th IEEE International Conference on Electronics, Circuits and Systems, (ICΕCS), vol. II, pp. 485-488, Croatia, Sept. 2002.
11. C. Efstathiou, H. T. Vergos, D. Nikolos, "Fast Parallel–Prefix Modulo 2n+1 Adders", 17th Conference on Design of Circuits and Integrated Systems (DCIS), pp. 65-70, Santander, Spain, Nov. 2002.
12. G. Dimitrakopoulos, H. T. Vergos, D. Nikolos, C. Efstathiou, "A Systematic methodology for Designing Area-Time Efficient Parallel-Prefix modulo 2n-1 adders", IEEE International Symposium on Circuits and Systems (ISCAS) pp. vol. 5, 225-228, Thailand, Bangcoc, May 2003.
13. D. G. Nikolos, D. Nikolos, H. T. Vergos, C. Efstathiou, "Efficient BIST Schemes for RNS data paths", IEEE International Symposium on Circuits and Systems (ISCAS), vol. 5, pp. 573-576, Thailand, Bangcoc, May 2003.
14. G. Dimitrakopoulos, H. T. Vergos, D. Nikolos, C. Efstathiou, "A family of parallel-prefix modulo 2n-1 adders", IEEE 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 326-336, Leiden, Netherlands, June 2003.
15. D. G. Nikolos, D. Nikolos, H. T. Vergos, C. Efstathiou, "An Efficient BIST scheme for High-Speed Adders", 9th IEEE International On-Line Testing Symposium" (IOLTS), pp. 89-93, Kos Island, Greece, July 2003.
16. C. Efstathiou, H. T. Vergos, G. Dimitrakopoulos, & D. Nikolos, "Efficient modulo 2n+1 tree multipliers for diminished-1 operands", 10th IEEE International Conference on Electronics, Circuits and Systems, ICΕCS 2003.
17. H. T. Vergos, C. Efstathiou, "Diminished-1 modulo 2n+1 squarer design", 7th EuroMicro Conference on Digital System Design, (DSD), Rennes, France 2004.
18. N. Sklavos, C. Efstathiou, "On the FPGA Implementation of HAVAL Hash Function", EUROCON 2005, Serbia & Montenegro, Belgrade, Nov. 2005.
19. K. Katzourakis, G. Kormentzas, K. Kontovasilis and C. Efstathiou, "An Open Distributed Software System for Providing Traffic Control and Resource Management Functionality in Heterogeneous ATM Core Networks", Proceeding of the Fifth Int. Network Conference (INC2005), pp. 63 -72, Samos, Greece.
20. P. Souras, N. Sklavos, C. Efstathiou, and A. Rjoub, "Networks Security: Risk Management and Economics in Information Technology", Proc. of ACIT 2005, Jordan, Dec. 6-8, 2005.
21. G. Dimitrakopoulos, D. G. Nikolos, H. T. Vergos, D. Nikolos, C. Efstathiou, "New Architectures For Modulo 2n-1 Adders", Proc. of ICECS 2005, Gammarth, Tunisia, Dec. 2005.
22. N. Sklavos, C. Efstathiou, "Area-Optimized Architecture & FPGA Implementation of the Pelican MAC Function", Proc. of the 2nd IEEE International Conference On
23. N. Sklavos, K. Touliou, C. Efstathiou, "Exploiting Cryptographic Architectures over Hardware Vs. Software Implementations: Advantages and Trade-Offs", Proc. of WSEAS Int. Conf. on AEE '06.
24. H. T. Vergos, C. Efstathiou, "Novel modulo 2n+1 multipliers", 9th EUROMICRO Conference on Digital System Design (DSD'06), pp. 168-175, 2006.
25. I. Voyiatzis, C. Efstathiou "Two-pattern generation based on Accumulators with 1’s Complement adders", In Proc. DTIS 2006.
26. H. T. Vergos and C. Efstathiou, "Efficient Modulo 2k+1 Squarers", XXI Conference on Design of Circuits and Integrated Systems (DCIS), Barcelona, Spain, 22-24, Nov. 2006.
27. A. Kakarountas, H. Michail, C. Goutis and C. Efstathiou, "Implementation of HSSec: a High-Speed Cryptographic Co-processor”, 12th IEEE Conference on Emerging Technologies and Factory Automation, Patras, Greece, Sept. 25-28, 2007.
28. N. Sklavos, C. Efstathiou, "SecurID Authenticator: On the Hardware Implementation Efficiency", Proc. of the 14th IEEE Int. Conf. on Electronics, Circuits and Systems (IEEE ICECS'07), Marrakech, Morocco, Dec. 11-14, 2007.
29. I. Voyiatzis, C. Efstathiou "An Efficient ARchitecture for Accumulator-Based Test Generation of SIC pairs", in Proc. of IEEE Int. Conf. on Design & Technology of Integrated Systems (DTIS 2008), Tozeur, Tunisia, March 26-28, 2008.
30. H. T. Vergos, D. Bakalis and C. Efstathiou, "Efficient Modulo 2n+1 Multi- Operand Adders", Proc. of 15th IEEE International Conference on Electronics, Circuits & Systems (ICECS), pp. 694-697, Malta, August 31-September 3, 2008.
31. I. Voyiatzis, H. Antonopoulou, C. Efstathiou, "A Low-Cost Optimal Time SIC Pair Generator", Proc. of 6th IEEE East-West Design and Test Symposium (EWDT), Kiev, 2008.
32. C. Efstathiou, I. Voyiatzis, N. Sklavos, "On the modulo 2n+1 multiplication for diminished-1 operands", Proc. of the 2nd IEEE Int. Conf. on Signals Circuits and Systems (SCS 2008), Tunisia, 7-11, Nov. 2008.
33. I. Voyiatzis, Antonopoulou H., C. Efstathiou, "Output Response Compaction in RAS-based Schemes", IEEE International Conference on Design & Technology ofIntegrated Systems in Nanoscale Technology (DTIS 2009), Cairo, Egypt, April 7-9, 2009.
34. C. Efstathiou, I. Voyiatzis, M. Prentakis, “Design methods for modulo 2n+1 multiply-add units”, Proc. of 7th IEEE East-West Design and Test Symposium (EWDTS), pp. 307-312, Moscow, Russia, Sept. 2009.
35. C Efstathiou, I. Voyiatzis, "Handling Zero in modulo 2n+1 subtraction", Proc. of the 3nd IEEE Int. Conf. on Signals Circuits and Systems (SCS09), Tunis, Nov. 2009.
36. I. Voyiatzis, Th. Haniotakis, C. Efstathiou, H. Antonopoulou, A Concurrent BIST architecture based on Monitoring Square Windows, Proc. of IEEE Conference on Design & Techology in Nanoscale Era, (DTIS), Tunisia, 2010.
37. C. Efstathiou, I. Voyiatzis, "On the modulo 2n+1 subtract units for weighted operands", Proc. of IEEE 22nd International Conference on Microelectronics (ICM), Cairo, Egypt, Dec. 2010.
38. C. Efstathiou, "Efficient modulo 2n+1 subtractors for weighted operands", 17th IEEE International Conference on Circuits and Systems (ICECS) Athens, Greece Dec. 2010.
39. C. Efstathiou, I. Voyiatzis, "On the diminished-1 modulo 2n+1 fused multiply-add units", Proc. of IEEE Conference on Design & Technology in Nanoscale Era, (DTIS), April 2011.
40. I. Voyiatzis, C. Efstathiou, H. Antonοpoulou, "Low–overhead two dimensional two pattern test", Proc. of IEEE Conference on Design & Technology in Nanoscale Era, (DTIS), April 2011.
41. I. Voyiatzis, C. Efstathiou, H. Antonοpoulou, "A Novel SRAM-Cell based Input Vector Monitoring Concurrent BIST architecture", Proc. of 16th IEEE European Test Symposium (ETS), Μay 2011.
42. C. Efstathiou, K. Pekmestzi, N. Axelos, "On the design of modulo 2n+1 multipliers", 14th Euromicro Conference on Digital Systems Design (DSD), Finland, Sept. 2011.
43. I. Voyiatzis, C. Efstathiou, C. Sgouropoulou, "ALU based address forRAMs", Proc. of IEEE Conference on Design & Technology in Nanoscale Era, (DTIS), April 2012.
44. I. Voyiatzis, C. Efstathiou, C. Sgouropoulou, "Test vector embedding in accumulators with stored carry in O(1) time", Proc. of IEEE Conference on Design & Technology in Nanoscale Era, (DTIS), April 2012.
45. I. Voyiatzis, C. Efstathiou, Y. Tsiatouhas, C. Sgouropoulou, "A novel architecture to reduce test time in march-based SRAM tests", Proc. of IEEE Conference on Design & Technology in Nanoscale Era, (DTIS), April 2012.
46. I. Voyiatzis, C. Efstathiou, D. Magos, C. Sgouropoulou, "Test set embedding into low-power sequences based on a traveling salesman problem formulation", Proc. of IEEE Conference on Design & Technology in Nanoscale Era, (DTIS), April 2012.
47. C. Efstathiou, N. Moschopoulos, C. Tsoumanis, C. Pekmestzi, "On the design of configurable modulo 2n±1 residue generators", 15th Euromicro Conference on Digital Systems Design (DSD), Turkey, Sept. 2012.
C. Efstathiou, Digital Design, New Technologies Publications, 2012 (in Greek)